The measurement of the gate leakage current of transistor devices (such as GaN transistor devices, for example) during production is necessary in order to separate between good and bad devices. For GaN transistor devices, for example, the gate leakage current may be measured with gate voltages ranging between −8 V and +6 V under several drain-source conditions and temperatures. The expected leakage current is very small (typically, in the nA range). During these tests all elements must be grounded, so that the high voltage spike cannot damage the device. Providing ESD protection structures at this stage would seriously impede the measurement of the gate leakage current. Accordingly, ESD protection structures are only connected after the wafer test, when the devices are assembled. However, during the pad bonding phase there is a potential risk of ESD failure for unprotected devices. Therefore, the current implementation practice shows considerable yield loss.